Best known methods for using Cadence Conformal LEC at Intel

In this paper we will explore how to use the Cadence Conformal LEC tool capabilities to verify different types of designs, based on the experiences of various projects at Intel. In particular, we will focus on the Conformal Ultra capability for verifying complex data-path synthesis and layout.. As an example, we will present a 1 Gigabit Ethernet chip with around 10 million standard cells. At first glance we thought that we would need to use the divide and conquer technique, and split the big design into smaller blocks in order to complete the verification. To our surprise, using the Conformal Ultra together with the effort "complete" we managed to verify the majority of the design in one flat run. In this presentation we will also discuss how to use the different Cadence Conformal LEC capabilities and what benefits they provide, describing numerous best-known-methods developed at Intel. The following learnings are based on using the tool on different types of designs. This kind of information can provide a significant saving of time and increase in user productivity. We will wrap up by presenting additional ideas for accelerating the design flow by further extensions to FEV tools like Cadence Conformal LEC.